SC23 Beowulf Bash Video Evidence

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Written by Douglas Eadline

Published: 07 December 2023

Hits: 4804

The SC23 Beowulf Bash was wildly successful, or was it wild and successful? You can judge for yourself because we have video evidence.

Thank you, Kiwi, for the video.

It should be noted that even though the video shows a fun main venue, by tradition, the Beowulf Bash always has rooms and locations where attendees can engage in conversation.

All this HPC fun was made possible by the Beowulf Bash Angels and Demons team and our wonderful supporting vendors. (That is not Ted Danson on the left.) One key demon did not make it for the team picture, but he is easily identified in the video.

First Experiences with Composable Hardware: An HPC User Perspective

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Written by Douglas Eadline

Published: 29 September 2022

Hits: 15423

Note: this paper was prepared for a conference that we decided not to attend (Okay, it was not accepted). It is written in a more formal style than the normal ClusterMonkey articles and is sponsored by the The Beowulf Foundation

Abstract

Popular homogeneous clustered HPC systems (e.g., commodity x86 servers connected by a high-speed interconnect) have given way to heterogeneous clusters comprised of multi-core servers, high speed interconnects, accelerators (often GPU based), and custom storage arrays. Cluster designers are often faced with finding a balance between purpose-built (tailored to specific problem domains ) and general use systems. Traditional cluster-based approaches, however, all share a hard boundary between internal server buses (mainly PCIe) and the rest of the cluster. In heterogeneous environments, the server boundary often creates inefficient resource management, limits solution flexibility, and heavily influences the design of clustered HPC applications. This paper explores the malleability of the GigaIO™ FabreX™ PCIe memory fabric in relation to HPC cluster applications. A discussion of emerging concepts (e.g., a routable PCIe bus) and hands-on benchmarks using shared GPUs will be provided. In addition, results of a simple integration with SLURM resource scheduler will be discussed as way to make composable/malleable computing transparently available to end-users. Keywords. Composable computing, malleable computing, PCIe, HPC cluster, SLURM, benchmark, FabreX , GigaIO, resource scheduler

The Y Event 2003 (formerly the Beowulf Bash)

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Written by Douglas Eadline

Published: 08 November 2023

Hits: 3979

The Beowulf Bash began in the late nineties when a bunch of Beowulf cluster geeks gathered for beer and pretzels during Supercomputing. Over the years, the success of the Beowulf Bash brand continued to grow at a steady rate, and the event is now an established and recognizable part of the annual SC experience.

Which makes it the perfect time to rebrand as the Y Event.

Of course, many of you may ask: why Y? Well, it seems that other letters were taken.

And then there is the church thing?

In any case, if attending SC23, just show up Monday night November 13 after the Gala. Services through 9pm to Midnight. Location: 1160 Lincoln Street, Denver

These are Not the Watts You Are Looking For

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Written by Douglas Eadline

Published: 14 April 2022

Hits: 9450

From the What's Watts Dept.

Some Clarity around TDP ratings

Managing power usage on multi-core processors has become an important aspect with modern computing systems. At the same time, finding an accurate specification of actual power usage has become more difficult. Knowing power usage is important in many areas and particularly when considering the efficiency of High Performance Computing (HPC) systems. In almost all modern CPUs and GPUs the only number that seems to give a hint about power usage is Thermal Design Power or TDP.

According to Wikipedia Thermal Design Power is defined as follows:

... is the maximum amount of heat generated by a computer chip or component (often a CPU, GPU or system on a chip) that the cooling system in a computer is designed to dissipate under any workload.

Some sources state that the peak power rating for a microprocessor is usually 1.5 times the TDP rating