AMD Opteron memory bandwidth (was Re: CPUs for a Beowulf)

[Greg Lindahl]

While we're reinventing the T3E, it's worth noting:

1) HT's current generation doesn't have ECC, it just has a CRC-check
and crashes when the check fails. That's kind-of OK for small systems,
but doesn't scale.
2) AMD's cache coherence protocol is snoopy, which doesn't scale.

I'd never heard the rumor about HT being the EV7+ bus (and I'd really
doubt it due to (1)), but I do know that AMD only bought the API
Networks technical team, not their technology. Digital/Compaq did have
a long-term technical collaboration with Samsung and AMD regarding the
EV6 bus.

And yes, using the Linux NUMA memory placement stuff is a substantial
improvement in Opteron performance for real apps.

-- greg

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