[Beowulf] A look at the 100-core Tilera Gx

Andrew Piskorski atp at piskorski.com
Tue Nov 3 15:34:41 EST 2009

On Tue, Nov 03, 2009 at 01:25:33PM -0500, Prentice Bisbal wrote:

>> With the new Gx series chips, FP code is still frowned upon, but
>> there is some FP hardware to catch the odd instruction without a
>> huge speed hit.

> I imagine this short-coming will limit the Tilera Gx's value to most of
> HPC community. This doesn't even mention DP performance.

I don't remember anything from the MIT RAW papers suggesting that the
technology can't handle floating point, so I assume their integer-only
focus was a business decision.  If their business is successful, I
imagine they'll offer a product intended for floating-point work some
years down the road (if they're still around by then, of course).

Andrew Piskorski <atp at piskorski.com>
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