AMD Opteron memory bandwidth (was Re: CPUs for a Beowulf)

[Richard Walsh]

On Tue Sep  9 2003, John Hearns wrote:

>On Mon, 8 Sep 2003, Jim Phillips wrote:
>
>> On Mon, 8 Sep 2003, Donald Becker wrote:
>> 
>> If you could connect those HyperTransport channels into a scalable mesh
>> then this sounds a lot like the good old Cray T3E design.  Drool...  It's
>> too bad that Red Storm won't be taking that route.  The T3E was so nice.
>
>The article I quoted from Digit Life floats the idea that AMD may be able 
>to make for Cray an Opteron with 4 Hypertransports, making a 3D mesh 
>possible. Is this just supposition?

Mmm ... with just 3 HT links per chip (one of which is attenutated .. IO)
I don't see how you can do a full 2D torus let alone a 3D which requires
6 per node.  Perhaps mesh here does not refer to the T3E's torus interconnect?
The 8-way SMP Opteron layouts that I have seen have edges.  Not withstanding 
this, Cray is custom engineering an MPP system with the Opteron as the base 
microprocessor and a proprietary interconnect for Sandia(?).  Anyone have 
more detail on this machine?

Regards,

rbw
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