Intel acquiring Pallas

Robert G. Brown rgb at
Thu Aug 28 12:05:52 EDT 2003

On Thu, 28 Aug 2003, Jeffrey B. Layton wrote:

> to bypass the PCI bottleneck. Of course they could also be after the Pallas
> parallel debuggers to integrate into their compilers (like you mentioned)
> or perhaps to help with debugging threaded code in the hyperthreaded chips.
>    Not that you mention it, this is a somewhat interesting development.
> I wonder what they're up to?

My guess is something like this, given what pallas does, but if this is
the case, they may be preparing to attempt a task that has brought
strong programmers to their knees repeatedly in the past -- create a
true parallel compiler.  A compiler where the thread library
transparently hides a network-based cluster, complete with migration and
load balancing.  So the same code, written on top of a threading
library, could compile and run transparently on a single processor or a
multiprocessor or a distributed cluster.  Or something.

Hell, they're one of the few entities that can afford to tackle such a
blue-sky project, and just perhaps it is time for the project to be
tackled.  At least they can attack it from both ends at once -- writing
the compiler at the same time they hack the hardware around.  But
they're going to have create a hardware-level virtual interface for a
variety of IPC mechanism's for this to work, I think, in order to
instrument it locally and globally with no particular penalty either
way.  Or, of course, buy SCI and start putting the chipset on their
motherboards as a standard feature on a custom bus.  Myricom wouldn't
like that (or Dolphin if they went the other way), but it would make a
hell of a clustering motherboard.


Robert G. Brown	             
Duke University Dept. of Physics, Box 90305
Durham, N.C. 27708-0305
Phone: 1-919-660-2567  Fax: 919-660-2525     email:rgb at

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