Memory - Revision history

Shewmaker at 06:48, 21 February 2006

2006-02-21T06:48:01Z

Shewmaker: swiotlb

2006-02-21T02:57:10Z

swiotlb

Shewmaker at 02:18, 21 February 2006

2006-02-21T02:18:36Z

New page

'''Error Detection And Correction'''

A cluster of systems with large amounts of RAM provides system integrators and administrators with an opportunity to become familiar with [http://en.wikipedia.org/wiki/Soft_error Soft Errors].

According to arch/*/kernel/mce.c and arch/*/kernel/traps.c, Linux kernels older than 2.6.16 will either see an uncorrectable bit error as a Machine Check Exception (MCE), print out a message with the DIMM bank, and panic; or as an NMI and continue on with a "Dazed" message. An NMI would be seen if MCE panic was disabled with the mce=off boot parameter.

There are new capabilites beginning with the 2.6.16 kernel. The code from the [http://bluesmoke.sourceforge.net EDAC] project was merged into the kernel as optional modules. The modules provide counters for correctable and uncorrectable errors, the ability to reset counters through sysfs, a reset counter - seconds since last reset, etc.

* [http://lwn.net/Articles/168972/ short LWN EDAC writeup]
* [http://lwn.net/Articles/168975/ edac.txt from the 2.6.16 kernel docs]

The Linux EDAC modules support the following memory controllers:

* AMD 76x
* Intel e752x
* Intel e7xxx
* Intel 82860
* Intel D82875P
* Radisys 82600

← Older revision		Revision as of 02:57, 21 February 2006
Line 18:		Line 18:
	* Intel D82875P		* Intel D82875P
	* Radisys 82600		* Radisys 82600
		+
		+
		+	'''I/O on 64-bit Systems With Large Amount of Memory'''
		+
		+	Part of the transition from 32-bit x86 to x86_64 with large amounts of memory involves handling I/O devices that only support 32-bit memory addresses. The AMD chipsets include a hardware IOMMU that makes everything work transparently. Intel EM64T (and IA64) chipsets do not include an IOMMU, so the Linux kernel implements a "software I/O translation buffer". The memory allocated to the swiotlb is made unavailable to normal processes, and some devices (such a NVIDIA graphic cards) may require more memory to be reserved in order to operate reliably. See the Linux kernel's documentation for information about the swiotlb boot parameter. This paragraph is a short summary of part of an [http://lwn.net/Articles/91870/ LWN DMA article] by Jonathan Corbet.

@@ Line 1: / Line 1: @@
-'''Error Detection And Correction'''
+==Error Detection And Correction==
 A cluster of systems with large amounts of RAM provides system integrators and administrators with an opportunity to become familiar with [http://en.wikipedia.org/wiki/Soft_error Soft Errors].
-According to arch/*/kernel/mce.c and arch/*/kernel/traps.c, Linux kernels older than 2.6.16 will either see an uncorrectable bit error as a Machine Check Exception (MCE), print out a message with the DIMM bank, and panic; or as an NMI and continue on with a "Dazed" message.  An NMI would be seen if MCE panic was disabled with the mce=off boot parameter.
+According to arch/*/kernel/mce.c and arch/*/kernel/traps.c, Linux kernels older than 2.6.16 will either see an uncorrectable bit error as a Machine Check Exception (MCE), print out a message with the DIMM bank, and panic; or as a Non-Maskable Interrupt (NMI) and continue on with a "Dazed" message.  An NMI would be seen if MCE panic was disabled with the mce=off kernel boot parameter.
 There are new capabilites beginning with the 2.6.16 kernel.  The code from the [http://bluesmoke.sourceforge.net EDAC] project was merged into the kernel as optional modules.  The modules provide counters for correctable and uncorrectable errors, the ability to reset counters through sysfs, a reset counter - seconds since last reset, etc.
-  * [http://lwn.net/Articles/168972/ short LWN EDAC writeup]
+*  [http://lwn.net/Articles/168972/ short LWN EDAC writeup]
-  * [http://lwn.net/Articles/168975/ edac.txt from the 2.6.16 kernel docs]
+*  [http://lwn.net/Articles/168975/ edac.txt from the 2.6.16 kernel docs]
 The Linux EDAC modules support the following memory controllers:
- * AMD 76x
+* AMD 76x
- * Intel e752x
+* Intel e752x
- * Intel e7xxx
+* Intel e7xxx
- * Intel 82860
+* Intel 82860
- * Intel D82875P
+* Intel D82875P
- * Radisys 82600
+* Radisys 82600
-'''I/O on 64-bit Systems With Large Amount of Memory'''
+==I/O on 64-bit Systems With Large Amounts of Memory==
-Part of the transition from 32-bit x86 to x86_64 with large amounts of memory involves handling I/O devices that only support 32-bit memory addresses.  The AMD chipsets include a hardware IOMMU that makes everything work transparently.  Intel EM64T (and IA64) chipsets do not include an IOMMU, so the Linux kernel implements a "software I/O translation buffer".  The memory allocated to the swiotlb is made unavailable to normal processes, and some devices (such a NVIDIA graphic cards) may require more memory to be reserved in order to operate reliably.  See the Linux kernel's documentation for information about the swiotlb boot parameter.  This paragraph is a short summary of part of an [http://lwn.net/Articles/91870/ LWN DMA article] by Jonathan Corbet.
+Part of the transition from 32-bit x86 to x86_64 with large amounts of memory involves handling I/O devices that only support 32-bit memory addresses.  AMD products include a hardware IOMMU that makes everything work transparently, for the most part.  Intel EM64T and IA64 products do not include an IOMMU, so the Linux kernel implements a "software I/O translation buffer".  The memory allocated to the swiotlb is made unavailable to normal processes, and some device drivers (such as the proprietary [http://download.nvidia.com/XFree86/Linux-x86_64/1.0-8178/README/appendix-l.html NVIDIA graphics driver]) may require more memory to be reserved in order to operate reliably.  See the Linux kernel's documentation for information about the swiotlb and iommu boot parameters.  Much of the information summarized in this paragraph was learned from an [http://lwn.net/Articles/91870/ LWN DMA article] by Jonathan Corbet.