<br><br><div><span class="gmail_quote">2008/2/25, Geoff Jacobs <<a href="mailto:gdjacobs@gmail.com">gdjacobs@gmail.com</a>>:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Bill Broadley wrote:<br> > I believe it's actually simultaneous, instructions from 2 different<br> > processes can run in the same cycle against 2 different register files.<br> ><br> > Other chips have vertical multithreading where only 1 process runs in<br>
> any given cycle.<br> <br> <br>Multiple threads residing in any particular stage of execution at any<br> particular time. If one thread stalls, the processor can proceed with<br> execution on the other thread.<br> <br>
Somewhat outside the bounds of this list, but would an in order<br> processor like Power 6 derive more benefit from SMT?</blockquote><div><br>Yes, and more than an out of order processor. A out of order processor, can reorder the instructions whenever a hazard occurs. A in order processor, on the other hand, has to wait. With SMT, it can switch to another thread.<br>
<br>And today memory access can stall up to hundreds of cycles, so any processor can hide this latency by switching to another thread.<br></div>But the you have to make sure the processor has enough cache and memory bandwidth to handle the increased memory traffic (like Sun Niagara).<br>
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