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<P>-------------- Original message -------------- <BR>From: "Finch, Ralph" <rfinch@water.ca.gov> <BR><BR>> [I know nothing! Just copy-and-paste from a Usenet group] <BR>> <BR>> Subject: Tilera to Introduce 64-Core Processor <BR>> Newsgroups: comp.arch, comp.arch.embedded, comp.sys.intel, <BR>> alt.comp.hardware.amd.x86-64, comp.sys.ibm.pc.hardware.chips <BR>> Date: Thu, 11 Oct 2007 11:02:14 -0700 <BR>></P>
<P>It is cool, but not as cool as it could be ... it has no FPUs like the development version or its academic predecessor, the RAW chip (or Intel's Polaris, for that matter). But the on-chip interconnection network is interesting and programmable, as is the pooled L3 cache. Eventually, as Moore's Law scaling drives up core counts, this kind of programmable mesh interconnect will replace what Intel and AMD currently provide. It a preview of the "many core" future.</P>
<P>rbw</P>
<P><BR>-- <BR><BR>"Making predictions is hard, especially about the future." <BR><BR>Niels Bohr <BR><BR>-- <BR><BR>Richard Walsh <BR>Thrashing River Consulting-- <BR>5605 Alameda St. <BR>Shoreview, MN 55126 <BR><BR>Phone #: 612-382-4620</P></BLOCKQUOTE>
!DSPAM:47137d46244572020149523!
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