<div>The future was here back in the late '90s with embedded DRAM in high-end NICs, then in 2000 in niche processor chips. The programming interfaces to take advantage of this, and the standardization of externally cascaded high-speed engines (100's of millions of searches/sec through 64K blocks) is still not widely standardized and in some cases the DRAM requires more standby power than SRAM, but can be up to 2x faster than SRAM alternatives. Low-latency high-speed memory access has been a requirement in fast switches and routers, but the technology is applicable to HPC/cluster computing as well.
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<div><a href="http://www.mosaid.com/corporate/products-services/ip/IPSOC2004_Unleashing_embDRAM_dec1404.pdf">http://www.mosaid.com/corporate/products-services/ip/IPSOC2004_Unleashing_embDRAM_dec1404.pdf</a><br> </div>
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<div>> This may well be the future. Small cores with ever growing "scratch"<br>space that uses explicit fetch/stores to main memory. Maybe some/most of<br>this will change from SRAM to a DRAM to make these local memories larger.
<br>Whatever the case, main storage needs to find its way closer to the<br>processing core. Double/Quad pumped buses and 128-bit memory channels can<br><span></span>only take us so far.<br> </div>