[Beowulf] HPC Market Question
kilian.cavalotti.work at gmail.com
Mon Jan 19 09:17:04 EST 2009
On Friday 16 January 2009 14:25:02 Jon Aquilina wrote:
> i havent done much digging in the transistor count but from people i have
> talked to in regards to the i7s the i7s are true quad cores im not sure
> what that means for the core 2 quads that came before the i7.
It means that Core2 Quad were architected as two dual-core chips sitting on
the same silicon die. Each pair of cores shared a L2 cache, but nothing was
shared (except the FSB, yikes!) amongst the four cores. In that respect, they
were often considered as "fake" quad-cores, and more as "dual-dual-cores".
On the contrary, Nehalem quad-cores feature four independent cores with no
intermediate hierarchical relationship, each with its own L2 cache. The four
of them also share a large L3 cache, which make it a "real" quad-core, as
The following summarizes the architectural differences between Core2 Quad
(Harpertown), Barcelona and i7 (Nehalem):
> > i7 is a pretty big discontinuity in intel's design. it'll be interesting
> > to see how smoothly they make it. but don't the first i7's actually
> > have _lower_ transistor count than current core2's?
Yes. Quad-core Nehalem is about 730M, whereas quad-core Penryn was over 800M.
This is mainly due to the cache size: 12MB L2 for Hapertown, 1MB L2 + 8MB L3
A: Because it messes up the order in which people normally read text.
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