[Beowulf] Nehalem Xeons 55** series

Tiago Marques a28427 at ua.pt
Mon Feb 23 15:22:49 EST 2009


On Mon, Feb 23, 2009 at 5:27 AM, Mark Hahn <hahn at mcmaster.ca> wrote:

> AMD Opteron "Shangai" 6MB L3 : 90% of peak
>> Intel "Nehalem" Core i7 : 95.2% of peak
>> Intel Itanium 2 : 95.6% of peak
>>
>
> interesting numbers, and Goto's efforts are always respected.
> it would be valuable to understand why, though.  I usually think
> of ia64 as being basically designed specifically to make this kind of
> hero-optimization possible.  but I wonder how well each of these chips does
> on low-to-medium quality user code and current compilers.

As I see it, plenty of bandwidth and an excellent choice of cache sizes,
latency and architecture. AMD had done a good job with Barcelona but didn't
follow up with further improvements(other than cache size) with Shangai.
Intel seems to have it the sweet spot.


>
>
>  It's a Core i7 but should give you an idea.
>>
>
> I suspect that lots of people are holding their breaths (and POs)
> waiting for Intel to release 2 (and 4?) socket nehalems.  it has to be a
> bit scary for AMD, since they're getting leapfrogged in the area
> of their traditional strength.  I don't have a sense for whether Goto's
> kind of tuning (beyond the ability of compilers, and relatively
> cache-friendly relative to flops) is terribly relevant to the market.

It's even worse for AMD in some other areas. Take a look at this:
http://it.anandtech.com/weblog/showpost.aspx?i=554
Best regards,
                                 Tiago Marques


>
>
> on the topic of memory bandwidth:
>  http://techreport.com/articles.x/16448
> makes it sound as if AMD knows they have a scaling problem with cache
> coherency, and have a solution queued.  does anyone know whether nehalem
> already has a probe filter?  or if AMD has mentioned anything about
> widening to a 3-4-dimm-per-socket memory interface?
>
> regards, mark hahn.
>

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