[Beowulf] Timers and TSC behaviour on SMP/x86

Mikhail Kuzminsky kus at free.net
Tue Jun 24 12:32:15 EDT 2008


As I remember, TSCs in SMP/x86 are synchronized by Linux kernels at 
the boot process. 

But the only message (about TSC) I see after Linux boot in dmesg (or 
/var/log/messages) in SuSE 10.3 w/2.6.22 default kernel on quad-core 
dual socket Opteron serever is

"Marking TSC unstable due to TSCs unsynchronized"

Does it means that RDTSC-based timer (I use it for microbenchmarks) 
will give wrong results ? :-(

Some additional information,
according Software Optimization Guide for AMD Familly 10h Processors
(quad-core) from Apr 4th, 2008:

Early each AMD core had own TSC. Now quad-core processors have one 
common clock source in NorthBridge (BTW, is it in this case integrated 
into CPU chip - i.e. includes integrated memory controller and support 
of HT links ? - M.K.) - for all the TSCs of CPUs (cores ? - M.K.).

The synchronization accuracy should be few tens cycles.

Mikhail Kuzminsky
Computer Assistance to Chemical Research Center
Zelinsky Institute of Organic Chemistry
Moscow  



   
_______________________________________________
Beowulf mailing list, Beowulf at beowulf.org
To change your subscription (digest mode or unsubscribe) visit http://www.beowulf.org/mailman/listinfo/beowulf

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.



More information about the Beowulf mailing list