[Beowulf] Teraflop chip hints at the future

Jim Lux James.P.Lux at jpl.nasa.gov
Wed Feb 14 12:51:21 EST 2007


At 09:17 AM 2/14/2007, Mark Hahn wrote:

>that's not the point, of course - even a small CPU on each dram chip 
>would add up to a profoundly powerful system.  for instance, take a 
>pretty mundane
>2-socket, 16GB workstation today and notice it's got probably 128 separate
>dram chips.  imagine if each of those had even a small onchip processor
>(say, 2-4Mt).  the potential is there for something quite useful (I 
>admit practical problems to getting dram vendors/industry to do such 
>a thing...)

I'm not sure you could put any processor (except maybe something like 
a microcontroller) into a DRAM design and keep the densities 
up.  There are all sorts of things that might bite you.. aside from 
thermal issues, I suspect that the number of mask layers, etc. is 
fairly small for DRAM.  The actual materials on the chip (doping 
levels, etc.) may not allow for a reasonably performing processor 
with reasonable feature sizes and thermal properties.  Getting the 
heat away from the junction is a big deal.

I think DRAMs are built with a maximum of 4 layers of interconnect 
with vias, while processors have a lot more layers and a much more 
sophisticated interconnect structure.


>>instance, because with DRAM you only read or write one location at time, very
>
>well, I have the impression that a lot of the power dissipated by modern
>chips is actually the external clock/PLL and drivers.

Each and every switch has some non-zero power associated with 
changing state. Sure, the core swings smaller voltages and energies, 
but a DRAM cell is a lot smaller than a flipflop or half-adder in the 
CPU, and only one is changing at a time, as opposed to thousands.


>  then again, a dram chip only dissipates a fraction of a watt (I 
> looked at a Micron 1Gb ddr2/667- it could possibly dissipate <.5 
> (all banks interleave), but normal
>back-to-back sequential activity would be only ~.3W.  that's for ddr2 at
>1.8V - ddr3 is 1.5 and I imagine the trend to lower voltages will continue.

To a point.. at some point, the leakage current starts to dominate 
over the switching energy as you make the features smaller and 
smaller.  around 1 Volt is "how low you can go"  voltage is important 
for switching energy because it goes as V^2*C, while power for 
leakage is linear in V.

A big advantage of integrating CPU and memory, though, is that you 
don't have to "go offchip" which saves a huge amount in 
drivers/receivers, etc.   Of course, this is why everyone is looking 
to integrated photonics and/or real high speed serial 
interconnects.  The I/O buffer might consume a hundred or thousand 
times more power than the onchip logic driving it.  Trading some more 
logic inside to serialize and deserialize, and do adapative 
equalization, in exchange for fewer "wires out of the chip" is a good deal.

Then, there's the speed of light problem.  Put two chips 10cm apart 
on a board, and the round trip time (say for address to get there and 
data to get back) is going to be in the nanoseconds area, even if the 
chip itself were infinitely fast.


James Lux, P.E.
Spacecraft Radio Frequency Subsystems Group
Flight Communications Systems Section
Jet Propulsion Laboratory, Mail Stop 161-213
4800 Oak Grove Drive
Pasadena CA 91109
tel: (818)354-2075
fax: (818)393-6875 


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