[Beowulf] Teraflop chip hints at the future

Jim Lux James.P.Lux at jpl.nasa.gov
Tue Feb 13 12:17:50 EST 2007


At 09:32 PM 2/12/2007, Mark Hahn wrote:
>>It looked like it did IEEE754 doubles.  Any Intel types out there 
>>to confirm/deny?
>what I don't really understand is why there aren't lots of groups doing
>this kind of exploratory chip.  is it just that any interesting chip
>tends to push design, circuit and fab boundaries all at the same time?
>
>>>>http://news.bbc.co.uk/1/hi/technology/6354225.stm
>
>frankly, I'm a bit embarassed by all these experts being quoted as saying
>that multicore is the brave new world.

Wouldn't Illiac IV be an example of multicore? (albeit SIMD, and I 
assume the terascale doesn't require all cores to do same ops in lockstep)
Maybe CM would be a better early example?



>  I saw one article that claimed that no OS existed to utilize 80 
> threads, and that no programmers could use them.

Jeeze.. pop up task manager in my desktop machine running WinXP, and 
there's gotta be at least 100 threads.. granted, some are blocked for 
I/O or timers, or not doing a whole lot

>(counterexample: Altix running Linux and OpenMP code from pretty mundane
>programmers...)
>
>amdahl's law: not just a good idea...
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James Lux, P.E.
Spacecraft Radio Frequency Subsystems Group
Flight Communications Systems Section
Jet Propulsion Laboratory, Mail Stop 161-213
4800 Oak Grove Drive
Pasadena CA 91109
tel: (818)354-2075
fax: (818)393-6875 


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