[Beowulf] Teraflop chip hints at the future
hahn at mcmaster.ca
Tue Feb 13 00:46:49 EST 2007
> Intel is stacking dram dice above the cpu as an L4 cache, but the article
stacking seems like a major hack - I'd rather think about how to do
processor-in-memory (perhaps zram?).
also, current production dram is around 1Gb/128MB, and the chip's
already got 400 KB of memory onchip. it's still really important
to have a substantial fan-out from cpu to memory for capacity.
> doesn't really
> explain how they plan to expand the off-chip bw other than by going to
isn't photonics still at the hand-waving stage? I was just noticing how 10G
XFP's have not gotten much cheaper over the past couple years. is there
really a prospect for wide and fast photonic links, given that copper links
are at ~3 Gb pretty easily? have people figured out how to mass-produce
photonic-chipped systems as efficient as copper PC boards and bumped chips?
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