[Beowulf] Teraflop chip hints at the future

Mark Hahn hahn at mcmaster.ca
Tue Feb 13 00:32:35 EST 2007


> It looked like it did IEEE754 doubles.  Any Intel types out there to 
> confirm/deny?

singles:

http://www.pcper.com/article.php?aid=363

IMO, the chip is mainly interesting to explore how much we can abandon
the von Neumann architecture as a whole, rather than stupidly putting
more and more of them onto a chip.  after all, the nearest-neighbor
latency (125 ps!) is comparable to cache or even register-file.
(admittedly, in this chip, the links are only 32b wide, which means 
any useful inter-PE message (say, at least a cachineline) would take
more than a couple cycles...

what I don't really understand is why there aren't lots of groups doing
this kind of exploratory chip.  is it just that any interesting chip
tends to push design, circuit and fab boundaries all at the same time?

>>> http://news.bbc.co.uk/1/hi/technology/6354225.stm

frankly, I'm a bit embarassed by all these experts being quoted as saying
that multicore is the brave new world.  I saw one article that claimed that 
no OS existed to utilize 80 threads, and that no programmers could use them.
(counterexample: Altix running Linux and OpenMP code from pretty mundane
programmers...)

amdahl's law: not just a good idea...
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