[Beowulf] Acceptable rad limits for cluster rooms?
greg.lindahl at qlogic.com
Mon Jun 19 13:54:05 EDT 2006
On Mon, Jun 19, 2006 at 06:02:45AM -0700, Jim Lux wrote:
> Bear in mind, though,
> that the processor itself is probably pretty susceptible to SEU, and
> doesn't have ECC internally.
Processor *caches* do have ECC, and since they're more susceptible
than the logic, this gets most of the benefit. And some peripheral
makers use ECC on all the rams in their chips, QLogic's FiberChannel
HBAs are an example.
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