[Beowulf] Re: Feedback on large pages in Linux (hahn at physics.mcmaster.ca)

Kevin Pedretti ktpedre at sandia.gov
Wed Jul 26 18:14:19 EDT 2006


> > below).  So, an app that accesses lots of little regions of memory
> > scattered all over the place will probably be hurt by using large
> > pages.
> 
> I find that statement a bit misleading; consider a case where I'm
> iterating through a 16M region, touching 1 word at 4k strides.
> 8x2M pages will be golden, whereas small pages would thrash badly.

My statement was too general.  Thanks for clearing it up with the two
examples (this one and in your other reply).

There are real apps that perform better with small pages on XT3.  This
is with the exact same *physical* memory layout, only difference being
the page size used.  I wouldn't expect this to happen if there were the
same number of 2-Mbyte and 4-Kbyte TLB entries.

> 
> the intel doc I looked at listed up to 128x4k and 64x2 or 4M pages.
> it didn't seem to address core2, though, which probably has more 
> than the pent-m.

I just opened up my Intel programmers guide, which I should have done in
the first place.  Here's the scoop:

Large Page DTLB:

  Pentium 4 and Intel Xeon: 64 entries, fully set associative,
                            shared with small page TLBs
  Pentium M: 8 entries, fully associative
  P6 family: 8 entries
  Pentium:   8 entries

Small Page DTLB:
  Pentium 4 and Intel Xeon: 64 entries, fully set associative,
                            shared with small page TLBs
  Pentium M: 128 entries, 4-way set associative
  P6 family: 64 entries
  Pentium:   64 entries

I haven't been able to find info on the core2.

Kevin



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