[Beowulf] Opteron downrates DDR400 to DDR333 performance?
hahn at physics.mcmaster.ca
Sun Feb 5 13:43:29 EST 2006
> http://www.valueram.com/datasheets/KVR400X72C3A_1G.pdf The specs describe
hmm, not the most explicit page...
> ECC memory module. The components on this module include eighteen 64M x
> 8-bit (16M x 8-bit x 4 Bank) DDR400 SDRAM in TSOP packages. The
my understanding is that the "ranks" (sometimes banks) that determine
how many/fast the dimms can run is really tied to the chip-select line
coming from the controller. since this is a double-sided dimm, I believe
each side uses one CS, so it counts as a 2-rank dimm to the controller.
I'm not sure the single/double sided -> 1/2-rank is a rule, though.
I'd guess that the best rule is chip-width * nchips=64 makes up a rank.
(registered dimms might not follow that either, since the register's
reason-for-existence is to present only one load to the bus/controller...)
actually, I just noticed that AMD also lists some quad-rank configs,
but only under buffered (s940) configs. however, the magic number
there also seems to be max 5 ranks at ddr400.
> (1) In the future, if I want to install ADDITIONAL memory in the OTHER two
> slots, will it be possible for me to retain DDR400 speed? If so, what
> constraints will there be on the additional memory? For example, could I
> use the same type?
according to the chart in the AMD doc, if you already have two 2-rank dimms
installed, further dimms need to be single-rank dimms to stay at ddr400.
the wording of the doc makes it seem like this is actually up to the board
vendor, though - how they configure the memory controller in bios.
it is, after all, one of those cases where faster is by definition closer
to the point of failure. what actually happens depends on the bios.
it looks like powertweak (powertweak.sourceforge.net/) doesn't yet have
any hooks into the dram or HT configuration registers on Hammer chips.
that's kind of a shame, because it looks to me like you could actually
modify them on a running system and get some interesting effects ;)
> (2) In my current configuration, using just two of the DIMMs described
> above, should the BIOS ECC chip kill setting be 'enabled' or 'disabled'?
hmm, I always assumed the chipkill feature meant that the memory controller
would map out a particular chip that was consistently bad. this is something
that would require help from the bios/SMI/OS, and so I've always disabled it.
but reading the AMD description, it seems to mean "72 vs 144b ECC". that is,
it's normal for people to have pairs of dimms installed, and that permits
wider and stronger ECC. I would, experimentally, try it. if I'm in a hurry
to get a machine running, I tend to turn off all features like this that
I don't necessarily need, but in this case, I can't really see where it
would go wrong on a system with paired ECC dimms.
regards, mark hahn.
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