[Beowulf] torus versus (fat) tree topologies

Craig Tierney ctierney at hpti.com
Wed Nov 17 11:24:50 EST 2004


On Tue, 2004-11-16 at 17:07, Mark Hahn wrote:
> > Mmm ... from your 2003 Hot Chips presentation on Elan 4 I see 231 
> > nanos.  Which is right, or are we talking about two different things?
> 
> AFAICT, the 25ns figure is for an individual 8-port xbar chip,
> and a full-sized switch is three stages of these.  but 6*25!=231.
> I believe there's at least one quadrics doc that quotes 300ns for 
> the switch.  perhaps the 231 number is derived from average latency
> (since some ports are just one xbar away)?
> 
> also, isn't SGI's numalink network a dual fat-tree?  they're claiming
> 1.1 us latency these days (though again, that might be averaged over
> all possible paths...)

Is that shmem latency or MPI latency?  I think that the MPI 
latency is closer to 2 u/s.

Craig

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