[Beowulf] RE: Vector processing on AMD 64

douglas@pop3.shore.net douglas at shell3.shore.net
Fri May 14 12:12:06 EDT 2004


Arthur:

I think you are refering to the SSE2 instructions available in (pretty
much) all x86 CPUs theses days. There are also the ACML math libraries for
Opterons which are optimized for BLAS routines. You may here these refered
to as the 'vectorized' libraries.

Go to developer.amd.com for links to the libraries and various
presentations.  In particular you might be interested in some of Tim
Wilken's presentations there.

doug


=======
Message: 6
Date: Thu, 13 May 2004 13:03:41 -0600
From: "Arthur H. Edwards" <edwardsa at plk.af.mil>
Subject: [Beowulf] Vector processing on AMD 64
To: beowulf at beowulf.org
Cc: "Arthur H. Edwards" <edwardsa at plk.af.mil>
Message-ID: <200405131903.i4DJ3gla004603 at knockout.kirtland.af.mil>
Content-Type: text/plain; charset=us-ascii

AMD has advertised that their 64 bit architectures have vector
registers. This was initially very exciting because eigensolvers are not
easily paralllized for medium-sized problems, but vectorize very well.
I say this based on experience with the CRAY-YMP where we saw speed-ups
ofrr 100 when we used a verctorized eigensolver. The Y-MP had, I think
128 vector registers, which could easily account for the 100 speed up.
Does anyone know

1. How many vector registers each of the AMD 64 bit CPU's has
2. Is there a source for the old CRAY vector library?

Art Edwards
-- 
Art Edwards
Senior Research Physicist
Air Force Research Laboratory
Electronics Foundations Branch
KAFB, New Mexico

(505) 853-6042 (v)
(505) 846-2290 (f)


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