[Beowulf] AMD’s Direct Connect Architecture

Richard Walsh rbw at ahpcrc.org
Thu Jul 1 19:07:18 EDT 2004


On Thu, 1 Jul 2004 13:29:15 , Greg Lindahl wrote:

>> Yes, yes ....  I was trying to point out the potential  
>> for confusion in looking just at the board and created by 
>> the fact that SMP-like sharing of hardware is blurring as 
>> designs share more or less of the components on a board, 
>
>Richard,
>
>SMP is SMP, and message passing is message passing. From a programming
>model view, the two are very different.  So I don't think anything is
>being blurred.

 Hi Greg,

 Not sure we were talking directly about parallel programming models
 before. I agree with the above statment if you substitute OpenMP for
 SMP .  To me SMP is a hardware design concept ... as in ... OpenMP 
 is to an SMP architecture as MPI is to a share-nothing architecture.

>> Is a dual Opteron motherboard with a memory channel from
>> each processor to its own memory and also hypertransport
>> memory sharing a 2-way system or just 2 1-way systems
>> on the same board?
>
>It's a 2 cpu SMP system with a NUMA memory system.

 Well, I guess I have trouble completely removing memory 
 design considerations from the notion of SMP. And if address
 space sharing of some kind (fully physical, partial physical,
 logical, RMA-type sharing supported in the interconnect) is 
 part of the SMP picture then it would seem we have to ask 
 ourselves what is being done to share the space because this 
 is what has performance/programming implications for the application.
 
 From what Mark seemed to suggest ...  a machine with identical
 (the intent of symmetric from his point of view) processors 
 that you could compile and run an OpenMP code on would
 qualify as SMP regardless of how the sharing of memory
 was implemented. 

 One can run a CAF program on the Cray T3E and all the memory 
 activity is taken care of for you. You just have to declare
 your Co-arrays. Requiring identical processors and programming
 model memory sharing alone in your definition of SMP you
 could call the Cray T3E an SMP machine under these circumstances. 

 This says, "I am not concerned about the cost of sharing memory
 on this architeture from my programs point of view ... I can
 still run my SMP-based programming model there." I am not sure
 I don't like this attitude even if it is agreed by some majority 
 to be definitionally correct.

 Mark will say perhaps that the address spaces are not shared 
 enough to qualify ... but if he does ... then the amount/kind of 
 sharing in the architecture has to be included in the definiion.
 
 I think I understand the points you both raise well enough.

 Thanks ;-),

 rbw

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