AMD Opteron memory bandwidth (was Re: CPUs for a Beowulf)
joachim at ccrl-nece.de
Wed Sep 10 03:39:26 EDT 2003
> > 2) AMD's cache coherence protocol is snoopy, which doesn't scale.
> That's a point often missed: in order to implement a HT switch for a SMP
> system, you need to implement something like a cache directory.
Yes, but only if you really want SMP characteristics (sequential consistency).
This is not mandatory for a HPC system if you can live with some kind of
message passing programming model (MPI).
Joachim Worringen - NEC C&C research lab St.Augustin
fon +49-2241-9252.20 - fax .99 - http://www.ccrl-nece.de
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