AMD Opteron memory bandwidth (was Re: CPUs for a Beowulf)

Jim Phillips jim at ks.uiuc.edu
Mon Sep 8 22:47:42 EDT 2003


On Mon, 8 Sep 2003, Donald Becker wrote:

> For a few processors, the HT-based cache coherency is fast enough to be
> ignored.  But for larger systems the only way avoid a big latency hit
> from the coherency traffic is to minimize the coherency traffic by
> having only the applications utilize it.  That means running the kernel
> from local memory, sharing only the locks and data structures needed for
> global I/O.
>
> Gee, suddenly the system starts looking like a cluster.  Sure, the
> application can now use global shared memory, and it's now efficient to
> implement a single file system view.  But all the approaches to making a
> cluster efficiently scalable can be directly applied to this type of
> SMP...

If you could connect those HyperTransport channels into a scalable mesh
then this sounds a lot like the good old Cray T3E design.  Drool...  It's
too bad that Red Storm won't be taking that route.  The T3E was so nice.

-Jim

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