A Petaflop machine in 20 racks?
James.P.Lux at jpl.nasa.gov
Mon Oct 20 17:50:56 EDT 2003
At 09:00 PM 10/19/2003 -0400, Christoph Best wrote:
>BTW, who or what is behind ClearSpeed? Their Bristol address is
>identical to Infineon's Design Centre there, and Hewlett Packard seems
>to have a lab there, too. If they have that kind of support, I am sure
>they thought hard before making these design choices, and it may just
>be tarketed at certain problems (vector/matrix/FFT-like stuff).
Off their web site...http://www.clearspeed.com/about.php?team
The CEO and president are marketing oriented (CEO: "he focused on taking
new technologies to market", President: "..successfully grown glabal sales
mangement and field application organizations and instrumental in creating
key partnership agreements".
The CTO (Ray McConnell) does parallel processing with 300K processors, etc.
VP Engr (Russell David) designed mixed signal baseband ICs for wireless
market. I didn't turn up any papers in the IEEE on-line library, but
that's not particularly signficant, in and of itself.
McConnell has a paper
shows architectures from PixelFusion, Ltd... SIMD core with 32 bit embedded
processor running a 256 PE "Fuzion block". Each PE has an 8 bit ALU and
2kByte PE memory... (sound familiar?)
From "Hot Chips 99"
James Lux, P.E.
Spacecraft Telecommunications Section
Jet Propulsion Laboratory, Mail Stop 161-213
4800 Oak Grove Drive
Pasadena CA 91109
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