A Petaflop machine in 20 racks?

Andrew Piskorski atp at piskorski.com
Fri Oct 17 21:41:25 EDT 2003


> > http://www.wired.com/news/technology/0,1282,60791,00.html

> From: "Jim Lux" <james.p.lux at jpl.nasa.gov>
> Subject: Re: A Petaflop machine in 20 racks?
> Date: Thu, 16 Oct 2003 16:46:19 -0700
>
> Browsing through ClearSpeed's fairly "content thin" website, one turns up
> the following:
> http://www.clearspeed.com/downloads/overview_cs301.pdf

> It also doesn't say whether the architecture is, for instance, SIMD.  It
> could well be a systolic array, which would be very well suited to cranking
> out FFTs or other similar things, but probably not so hot for general
> purpose crunching.

If it is SIMD, this sounds rather reminiscent of the streaming
supercomputer designs people hope to build using SIMD commodity GPU
(Graphics Processing Unit) chips, and Peter Schroeder's 2002 "Hacking
the GPU" class at CalTech.  I don't know much of anything about it,
but these older links made for some interesting reading:

  http://www.cs.caltech.edu/courses/cs101.3/
  http://www.cs.caltech.edu/cspeople/faculty/schroder_p.html

  http://merrimac.stanford.edu/whitepaper.pdf
  http://merrimac.stanford.edu/resources.html

  http://graphics.stanford.edu/~hanrahan/talks/why/

I am really not clear how any of that relates to vector co-processor
add-on cards like the older design mentioned here (I think FPGA
based):

  http://aggregate.org/ECard/

nor to newer MIMD to SIMD compiling technology (and parallel
"nanoprocessors"!) like this:

  http://aggregate.org/KYARCH/

-- 
Andrew Piskorski <atp at piskorski.com>
http://www.piskorski.com
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