A Petaflop machine in 20 racks?

Alan Scheinine scheinin at crs4.it
Fri Oct 17 04:35:48 EDT 2003


   I have not read carefully descriptions of the Opteron architecture
until a few minutes ago.  I was not able to find a picture of the
layout in silicon at the AMD site, I found a picture at Tom's Hardware.

 http://www.tomshardware.com/cpu/20030422/opteron-04.html

The page before shows that 50 percent of the silicon is cache.
Of what is not cache, it seems that the floating point unit
occupies about 1/6 or 1/7th of the area, moreover, the authors
Frank Voelkel, Thomas Pabst, Bert Toepelt, and Mirko Doelle
describe the Opteron as having three floating point units,
FADD, FMUL and FMISC.  Just counting FADD and FMUL and considering
the entire area of the Opteron, using 2 GHz for the frequency,
that would be about 12 FP units times 2 GHz, 24 GFLOPS.  So it
is doable.  I do not know the depth of the pipeline, but it is
likely it is deep.  How do you keep the pipeline full?  PCI is
around 0.032 Giga floating point words per second?  The entire
memory subsystem needs to be changed drastically.  Moreover,
whereas integer units might be used to solve problems that are
logically complex, floating point problems are typically ones
that use a large amount of data, more than what can fit into cache.

But you-all knew that already,
Alan Scheinin
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