Cheap PCs from Wal-Mart

Jim Lux James.P.Lux at jpl.nasa.gov
Wed Jun 4 00:41:19 EDT 2003


From: "Mark Hahn" <hahn at physics.mcmaster.ca>
To: "Jim Lux" <James.P.Lux at jpl.nasa.gov>
Sent: Tuesday, June 03, 2003 4:32 PM
Subject: Re: Cheap PCs from Wal-Mart


> > > > This is really a first order approximation. You'd have to look at
> > > > peripheral power, memory power, and power supply conversion and
power
> > > > distribution efficiency.  Peripherals and memory probably scale with
> > memory
> > > > speed fairly linearly.
> > >
> > > huh?  do you mean "the P4 drives ram much faster and so the ram
> > > will also dissipate more power"?
> >
> > Precisely.. CMOS, to a first order, has power dissipation proportional
to
> > clock frequency. Cycle the bus at 200 MHz and it draws twice as much
power
> > as cycling the bus at 100 MHz.  I don't know if the P4 or C3 have the
same
> > bus width, too? Wider buses draw more power (for the line
> > drivers/receivers).
>
> your basic premise in all of this is that you have some kind of
> computational task which simply doesn't need memory bandwidth
> or FP power.  yes, desktop/server CPUs are not at all optimized
> for that kind of load, and never will be, so why aren't you using
> a mips or arm chip?


Because you want to take advantage of the millions (billions?) of dollars
being spent on development for the consumer market. Sure, you could use a
more highly optimized chipset, or you could even spend a few tens of
millions of dollars and design your own. However, you'd not be able to reap
the benefits of:
1) Extensive defacto testing of the consumer chip's internal logic...
2) Amortization of development costs across literally millions of units
3) Development tools at low cost
4) Large numbers of people familiar with the instruction set, and the
development tools.

One could, of course, acquire all these things with other approaches,
however, at some point you have to decide, for a low volume application,
whether you want to spend your money on one-off development, or just buying
some number more processors. The latter approach has a graceful degradation
path in the event of failures.

Granted, this grossly oversimplifies what goes into those sorts of
applications, but, the real point is that the fastest chip isn't always the
best system solution.


> > It's a huge issue... The efficiency of the PS is lower at 3.3V than at
5V or
> > 12V, for instance.  As far as the CPU core voltage regulator, the same
> > applies... If you push power through anything, you're going to have more
IR
> > losses at 1.8V than at 2.5V.  There's only so much copper available on
the
> > board to carry the current, and the pin or ball is only so big.  On
chip,
>
> except that we're talking about a whole *plane* devoted to VCC
> (which can be modeled as a rather large wire), and literally hundreds
> of pins.  I'm guessing that loss is on the order of 2-5%.

People are more than willing to spend hundreds of thousands of dollars to
increase efficiency 5% on spaceflight applications. If all you got is 100W
from solar panels, constrained by fundamental limits (how far you are from
the sun, how much mass you're willing to devote to panels, etc.), then there
are situations where 5% is a very big deal.  Especially if it makes a big
difference in thermal management.

>
> > However, consider.. a contact/trace resistance of 5 milliohms, carrying
a
> > current of 20 amps, disspates 2 Watts... 5 mOhm is pretty darn low..
> > especially for a pin only 25 mils on a side.
>
> except when there are 100 of them.
P4, 478 pin package, 85 power pins, 180 ground pins.. who knows what sort of
bond wires connect them internally, etc.

Sure, you've got lots of pins, and lots of copper on the board, but, still,
running 100W in small area is no trivial matter.


>
> as I said, I'm not denigrating the value of low-power chips in certain
> domains.  I just don't think there's a good argument for compute clusters
> of low-power chips, at least not general-purpose ones.  and for special
> purpose, I'd suggest offloading all the hard stuff onto an FPGA or the
like,
> and using a CPU that doesn't even pretend to be competitive...

Aha.. but isn't the whole point of cluster computing a'la Beowulf to accept
some inefficiencies over a custom design in exchange for very attractive
pricing of a commodity component? Otherwise, wouldn't everyone just go out
and buy N-way Crays?

>
> regards, mark hahn.
>

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