becker at scyld.com
Wed Jul 2 13:47:58 EDT 2003
On Wed, 2 Jul 2003, Jack Wathey wrote:
> I need some advice about how to handle some ambiguous results from
> memtest86. I also have some general questions about bios options
> related to ECC memory.
> The boards are Gigabyte Technologies model GA7DPXDW-P,
> ...Testing in batches of 3 sticks per motherboard, nearly 100% failed
My immediate reaction is that you have a motherboard that has memory
configuration restrictions. A typical restriction is that can only use
two DIMMs when they are "double sided" (with two memory chips per signal
line instead of one) or have larger-capacity memory chips.
My second reaction is that you are running the chips too fast for ECC,
either because the serial EEPROM has been reprogrammed to claim that the
chips are faster or the BIOS settings have been tweaked. Remember than
a ECC memory system is slower than the same chips without ECC!
> In the bios for my GA7DPXDW-P motherboards, there are these 4
> alternatives for the SDRAM ECC Setting:
> Check only
As the memory read is happening, start checking the data. If the check
fails, interrupt later.
> Correct Errors
When the memory read is started, check the data. Hold the result
until the check passes or the data is corrected.
> Correct + scrub
Correct read data as above, holding the transaction and writing
corrected data back to the DIMM if an error is found.
> I'm pretty sure I understand what 'Disabled' does. Can anyone
> explain to me what the others do, and how they differ? Also, if ECC
> correction is enabled, does this slow down the machine in any way?
Yes. The typical cost is one clock cycle of read latency.
It might seem obviously easy to overlap the ECC check when it usually
passes, but you can't really hide all of the cost. The memory-read path is
Donald Becker becker at scyld.com
Scyld Computing Corporation http://www.scyld.com
914 Bay Ridge Road, Suite 220 Scyld Beowulf cluster system
Annapolis MD 21403 410-990-9993
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