Fortran compilers for Linux/mpich

Don Holmgren djholm at fnal.gov
Fri Nov 23 14:10:59 EST 2001



On Fri, 23 Nov 2001, Craig Tierney wrote:

> On Fri, Nov 23, 2001 at 02:46:38PM +0100, Steven Berukoff wrote:
> > 
> > Yes, you can use the Intel compilers to compile code for Athlons.  Since
> > the AMD instruction set supports SSE, you can include Pentium 3
> > optimizations that improve performance a bit. 
> 
> Does anyone know how similar/different are the SSE instructions
> are implemented Athlon vs. P3/P4 chips?  Are the operational counts
> the same or is one slower than he other?
> 


At the very bottom of the page,
   http://qcdhome.fnal.gov/sse/
I have a table with cycle counts posted for a number of matrix-matrix
and matrix-vector routines as measured on a P-III (Coppermine), P4, and
an Athlon MP.  Times are posted for both a pure-C version of each
routine, built with gcc, as well as for an SSE version.  The sources
for each are available at
   http://qcdhome.fnal.gov/sse/catalog.html

The results are a mixed bag, with each flavor processor sometimes first,
second, or third.  I'm using only a small subset of SSE - mostly shufps,
addps, mulps, with a few xops, movaps, and movups thrown in.  I haven't
timed individual instructions on all three processors.

Don Holmgren
Fermilab


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