newbie requests advice.

Zao Yang zyang at bigbend.ece.ucsb.edu
Tue Jun 19 15:30:42 EDT 2001


On Tue, 19 Jun 2001, Adam Shand wrote:

> 
> > we built a linux farm to do verilog simulations at the company I'm working
> > for. as far as I know, all HDL simulators are single threaded, I don't
> > know how would beowulf help you.
> 
> ah. okay doesn't surprise me but bummer.
> 
> > we are using a tool called LSF, from Platform Computing I think, which
> > can monitor all the machines in our server farm and automatically
> > dispatch simulation jobs to one of them when the job queues, server
> > load, memory and other constraints are met.
> 
> yep lsf is one of the tools i've been pointed to by our developers.  does
> it support transparent checkpointing and migration, that was one of the
> features of condor i really liked (though the requirement of relinking the
> apps makes it unfeasible).
> 
> any comments on how it compares with other tools?

I don't know if lsf support checkpoint saving and restarting.  we use the
verilog simulator to do this. I don't believe lsf support process
migration. I never found the need to migration a simulation job from one
machine to another. I'm not sure how useful this feature is for HDL
simulation.

sorry, I haven't used other load sharing tools. 

> 
> > our experience shows that the limitation on 3GB memory is only
> > problematic if you are running gate level simulation of a very large
> > asic. but, in that case, you would have the same problem with any
> > 32bit processor anyways.
> 
> yep that's exactly the problem we have is at the end of a project when we
> have to do gate level simulations.
> 
I only worked on one project where we ran out of addressable space in gate
level simulation. we solved problem by simulating the chip in parts.
depending on your design flow. this may or may not be applicable to you.
we only use gate level simulation to check reset circuits and some basic
check to ensure synthesis tool didn't generate some crazy logic. so
simulating the chip in parts is not big risk. I know some people use gate
level simulation with back-annotated timing to check timing as well. in
that case, simulating in parts in not good idea. but if proper static
timing analysis is done, you shouldn't have to use back-annotation. so
there are ways to solve a problem other than throwing hardware at it.

// zao


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